1. Field of the Invention
The invention relates to a manufacturing method of compound semiconductor device operating at high frequencies, specifically to a method which prevents chipping of compound semiconductor substrate during dicing process, and a compound semiconductor device made by the manufacturing method.
2. Description of the Related Art
The demand for high frequency devices has been rapidly increasing due to the expanding market for portable telephones and digital satellite communication equipment. Many of such devices include field effect transistors (referred to as FET, hereinafter) employing a gallium arsenide (referred to as GaAs, hereinafter) substrate because of its excellent high frequency characteristics. Typical application in this field includes local oscillation FETs and monolithic microwave integrated circuits (MMIC) in which a plurality of FETs are integrated.
In a typical semiconductor device manufacturing process, a semiconductor wafer in which semiconductor devices have been formed must be separated into individual devices. The most popular method to cut the wafer is to use a dicing saw. Such a method is well know and described in may publications including Japanese Laid Open Patent Publication No. Sho 60-34827.
FIG. 1 shows a conventional alignment of a GaAs wafer 12 with respect to a mask 11 having individual chip patterns 13. The GaAs wafer 12 is positioned with respect to the mask 11 using an orientation flat OF of the GaAs wafer as a positioning reference. Specifically, an edge of the mask 11 and the orientation flat OF is aligned so that the two directions are parallel to each other or perpendicular to each other. In such a configuration, all the chip patterns are aligned in directions parallel to and perpendicular to the edge of the mask 11. As indicated by an arrow in FIG. 1, the orientation flat OF is generally formed in a direction normal to a [0 {overscore (1)} {overscore (1)}] direction of the GaAs lattice. The surface of the GaAs wafer 12 is a (1 0 0) plane of the GaAs lattice and is exposed in a photolithographic process to form semiconductor devices such as GaAs FETs. The notation of surfaces and planes described in this specification is based on Miller indices.
During a dicing process of the GaAs wafer 12, a dicing blade is first positioned on a dicing region 14 formed on the primary plane of the GaAs wafer 12, and then cuts the GaAs wafer 12 along the dicing region 14. Because of chipping, a typical width of the dicing region 14 is 50 μm. Other operational parameters of dicing blades in this process include a cutting speed of about 6 mm/sec and a blade spin rate of about 30000 to 35000 rpm. After dicing, the GaAs wafer 12 which have been cut by the dicing blade is rinsed with water and then dried before being sent to a bonding process.
According to this conventional alignment of the mask, the chip patterns and the wafer, the wafer is diced in a direction parallel to or normal to the [0 {overscore (1)} {overscore (1)}] direction of the wafer. On a (1 0 0) plane of the GaAs lattice, the cleavage direction is either parallel to or normal to the [0 {overscore (1)} {overscore (1)}] direction. Thus, when the wafer is cut along a direction parallel to the [0 {overscore (1)} {overscore (1)}] direction, cleavage may easily occur along a direction normal to the cutting direction. Accordingly, when the GaAs wafer 12 is diced along this direction, a large amount of chipping occurs along this direction because of the cleavage induced by stresses generated at a contact between the rotating dicing blade and the surface of the GaAs wafer 12. Chipping is a crack formation at the surface cut by the dicing blade and leads to reduced yield of the manufacturing process. Because of the chipping, the width of the dicing region 14 should be wider than otherwise required, or the cutting speed should be slow so as not to induce a large amount of chipping.